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DATE
2009
IEEE

Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing

9 years 5 months ago
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of quasi-cyclic (QC) LDPC codes that takes advantage of the high bandwidth of the embedded memory blocks (called Block RAMs in a Xilinx FPGA) by packing multiple messages into the same word. We describe a vectorized overlapped message passing algorithm that results in 3.5X to 5.5X speedup over state-of-theart FPGA implementations in literature.
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella
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