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DAC
1997
ACM

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures

9 years 3 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexed addressing mode, stack-allocated variables must be accessed by allocating address registers and performingaddress arithmetic. Subsuming address arithmetic into auto-increment/decrement arithmetic improves both the performance and size of the generated code. Our objective in this paper is to provide a method for comprehensively analyzing the performance benefits and hardware cost due to an auto-increment/decrement feature that varies from ,l to +l, and allowing access to k address registers in an address generator. We provide this method via a parameterizable optimization algorithm that operates on a procedure-wise basis. Hence, the optimization techniques in a compiler can be used not only to generate efficient or compact code, but also to help the designer of a custom DSP architecture make decisions on a...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
Added 06 Aug 2010
Updated 06 Aug 2010
Type Conference
Year 1997
Where DAC
Authors Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
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