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DAC
1997
ACM
10 years 2 months ago
Power Management Techniques for Control-Flow Intensive Designs
This paper presents a low-overhead controller-based power managementtechnique that re-specifies control signals to reconfigure existing multiplexer networks and functional units t...
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazuto...
DAC
1997
ACM
10 years 2 months ago
Technology-Dependent Transformations for Low-Power Synthesis
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
Rajendran Panda, Farid N. Najm
DAC
1997
ACM
10 years 2 months ago
Formal Verification of a Superscalar Execution Unit
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
Kyle L. Nelson, Alok Jain, Randal E. Bryant
DAC
1997
ACM
10 years 2 months ago
Formal Verification of FIRE: A Case Study
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl P...
DAC
1997
ACM
10 years 2 months ago
SPIE: Sparse Partial Inductance Extraction
Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore...
Zhijiang He, Mustafa Celik, Lawrence T. Pileggi
DAC
1997
ACM
10 years 2 months ago
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries
This paper describes a fully automatic standard-cell layout synthesis system, CELLERITY. The system is flexible in supporting a wide variety of process technologies and a range of...
Mohankumar Guruswamy, Robert L. Maziasz, Daniel Du...
DAC
1997
ACM
10 years 2 months ago
Low Energy Memory and Register Allocation Using Network Flow
This paper presents for the first time low energy simultaneous memory and register allocation. A minimum cost network flow approach is used to efficiently solve for minimum energy...
Catherine H. Gebotys
DAC
1997
ACM
10 years 2 months ago
A C-Based RTL Design Verification Methodology for Complex Microprocessor
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon ...
DAC
1997
ACM
10 years 2 months ago
Cluster Refinement for Block Placement
Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
DAC
1997
ACM
10 years 2 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
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