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ICCAD
2003
IEEE

Analytical Bound for Unwanted Clock Skew due to Wire Width Variation

14 years 15 days ago
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation forms a bottleneck preventing further improvement on clock frequency. Impact from intra-chip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature. Through wire shaping analysis, we establish an analytical bound for the unwanted skew due to wire width variation which is the dominating factor among interconnect variations. Experimental results on benchmark circuits show that this bound is safer, tighter and computationally faster than similar existing approach.
Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2003
Where ICCAD
Authors Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu
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