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ICCAD
2003
IEEE
151views Hardware» more  ICCAD 2003»
10 years 4 months ago
On Compacting Test Response Data Containing Unknown Values
The design of a test response compactor called a Block Compactor is given. Block Compactors belong to a new class of compactors called Finite Memory Compactors. Different from spa...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janu...
ICCAD
2003
IEEE
193views Hardware» more  ICCAD 2003»
10 years 4 months ago
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits
: This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and ...
Lei Yang, C.-J. Richard Shi
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
10 years 4 months ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
10 years 4 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
10 years 4 months ago
An Algorithmic Approach for Generic Parallel Adders
Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Che...
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
10 years 4 months ago
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics
As research begins to explore potential nanotechnologies for future post-CMOS integrated systems, modeling and simulation environments must be developed that can accommodate the c...
Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
10 years 4 months ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
10 years 4 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
ICCAD
2003
IEEE
99views Hardware» more  ICCAD 2003»
10 years 4 months ago
A Probabilistic Approach to Buffer Insertion
This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flo...
Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati,...
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