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ICCAD
1996
IEEE

Analytical delay models for VLSI interconnects under ramp input

9 years 5 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical RLC interconnectionswith ramp input, Elmore delay can deviate by up to 100% or more from SPICEcomputed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4% of SPICE-computed delay, and models based on both first and second moments are within 2:3% of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of source-sink delays in arbitrary interconnect trees.
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where ICCAD
Authors Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
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