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DAC
1995
ACM
13 years 8 months ago
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate ...
Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John...
DAC
1994
ACM
13 years 9 months ago
Rectilinear Steiner Trees with Minimum Elmore Delay
We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3, 13] has established Elmore delay as a high delity estima...
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCo...
ICCAD
1996
IEEE
122views Hardware» more  ICCAD 1996»
13 years 9 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 9 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ISCAS
1999
IEEE
88views Hardware» more  ISCAS 1999»
13 years 9 months ago
Signal waveform characterization in RLC trees
- Closed form solutions for the 50% delay, rise time, overshoot characteristics, and settling time of signals in an RLC tree are presented. These solutions have the same accuracy c...
Yehea I. Ismail, Eby G. Friedman, José Luis...
GLVLSI
1999
IEEE
85views VLSI» more  GLVLSI 1999»
13 years 9 months ago
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric
The Elmore delay is the metric of choice for performancedriven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. ...
Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawr...
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
13 years 10 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao