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DAC
2006
ACM

Architecture-aware FPGA placement using metric embedding

10 years 1 months ago
Architecture-aware FPGA placement using metric embedding
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from graph embedding and metric geometry. Our approach, CAPRI, can be viewed as an embedding of a graph representing the netlist into a metric space that is representative of the FPGA. First, we develop an analytic metric of distance that models delays along the FPGA routing grid. We then embed a netlist into the defined metric space using matrix projections and online bipartite matching. Experimental comparisons with the popular FPGA tool, VPR, show that with CAPRI's initial solution, the resulting placements show median improvements of 10% in critical path delays for the larger MCNC benchmarks. Total placement runtime is also improved by 2x on average. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids Genera...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi
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