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VLSISP
2008

Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

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Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware l...
Stefan Tillich, Martin Feldhofer, Thomas Popp, Joh
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where VLSISP
Authors Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl
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