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GLOBECOM
2007
IEEE

A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders

9 years 20 days ago
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processing unit computes the bit-to-check node messages sequentially, while the computation of the check-to-bit node messages is broken up into several steps. A stand-alone decoder architecture, and a decoder architecture for a concatenated detector-decoder system are presented. The proposed stand-alone decoder architecture requires significantly less memory compared to other known serial architectures. The hardware requirements are reduced even further for the concatenated detector-decoder system.
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where GLOBECOM
Authors Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon Wei
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