Implementing LDPC Decoding on Network-on-Chip

Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to their ability to achieve near Shannon-limit communication channel capacity, the computational complexity of the decoder is a major concern. LDPC decoding consists of a series of iterative computations derived from a message-passing bipartite graph. In order to efficiently support the communication intensive nature of this application, we present a LDPC decoder architecture based on a network-on-chip

• Type: Conference
• Year: 2005
• Where: VLSID
• Authors: Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin
• Keywords: Communication Channel Capacity, Computer Architecture, Error Correcting Codes, Parity Check Codes, VLSID 2005