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2006
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Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream

9 years 7 months ago
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC techniques require direct access to the CPU-cache bus, meaning that the checking hardware (generally called a watchdog processor (WP)) has to be on-chip. However, an on-chip WP directly accessing the CPU-cache bus has several disadvantages: (i) it reduces CPU performance by increasing the load on this bus; (ii) it cannot be used with commodity processors; (iii) if introduced into commodity processors, it will use up appreciable chip real estate, but may be unnecessary in most environments that do not have significant transient error rates. On the other hand, if an off-chip CFC technique can be developed that imposes minor hardware overheads on the processor chip, then such a WP can be plugged onto the external system bus when needed for concurrent checking, and will have none of the above disadvantages. Suc...
Federico Rota, Shantanu Dutt, Sahithi Krishna
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where DFT
Authors Federico Rota, Shantanu Dutt, Sahithi Krishna
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