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DAC
2012
ACM

Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs

7 years 12 months ago
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization methodology to alleviate mechanical reliability issues in 3D IC. First, we analyze the stress induced by chip/package interconnect elements, i.e., TSV, µ-bump, and package bump. Second, we explore and validate the principle of lateral and vertical linear superposition of stress tensors (LVLS), considering all chip/package elements. This linear superposition principle is utilized to perform full-chip/package-scale stress simulations and reliability analysis. Finally, we study the mechanical reliability issues in practical 3D chip/package designs including wide-I/O and block-level 3D ICs. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuit]: Design Aids General Terms Design Keywords 3D IC, TSV, stress, mechanical reliability, chip/package co-analysis
Moongon Jung, David Z. Pan, Sung Kyu Lim
Added 29 Sep 2012
Updated 29 Sep 2012
Type Journal
Year 2012
Where DAC
Authors Moongon Jung, David Z. Pan, Sung Kyu Lim
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