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ACST
2006

A combinatorial group testing method for FPGA fault location

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A combinatorial group testing method for FPGA fault location
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, fault isolation is realized without requiring additional test vectors or data coding schemes. Hence the reprogrammability of Field Programmable Gate Arrays (FPGAs) is utilized to examine CED alternatives in succession. Results show that for a reprogrammable device with one million resources, where 50% of the resources are used on an average by the target application, fault isolation can be achieved in as few as 28 iterations. The effect of resource utilization, the number of competing candidate solutions, and the number of unit resources are analyzed and the performance of a halving-based algorithm for fault isolation are quantified.
Carthik A. Sharma, Ronald F. DeMara
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2006
Where ACST
Authors Carthik A. Sharma, Ronald F. DeMara
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