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» A combinatorial group testing method for FPGA fault location
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ACST
2006
10 years 4 months ago
A combinatorial group testing method for FPGA fault location
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of m...
Carthik A. Sharma, Ronald F. DeMara
JCO
2008
85views more  JCO 2008»
10 years 2 months ago
Locating and detecting arrays for interaction faults
The identification of interaction faults in component-based systems has focussed on indicating the presence of faults, rather than their location and magnitude. While this is a va...
Charles J. Colbourn, Daniel W. McClary
ITC
2003
IEEE
162views Hardware» more  ITC 2003»
10 years 7 months ago
FPGA Interconnect Delay Fault Testing
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
Erik Chmelar
CSREAESA
2008
10 years 4 months ago
BIST-BASED Group Testing for Diagnosis of Embedded FPGA Cores
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
Alireza Sarvi, Carthik A. Sharma, Ronald F. DeMara
FPL
2004
Springer
130views Hardware» more  FPL 2004»
10 years 8 months ago
BIST Based Interconnect Fault Location for FPGAs
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
Nicola Campregher, Peter Y. K. Cheung, Milan Vasil...
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