Sciweavers

Share
ASPDAC
2007
ACM

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

10 years 1 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail
Added 12 Aug 2010
Updated 12 Aug 2010
Type Conference
Year 2007
Where ASPDAC
Authors Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
Comments (0)
books