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DAC
1997
ACM

Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets

11 years 9 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the existence of a deadlock free schedule. The presented algorithm fits in the design flow of GRAPE, an environment for the emulation and implementation of digital signal processing (DSP) systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Reducing the size of data buffers is of high importance when the application will be mapped on Field Programmable Gate Arrays (FPGA), since register resources are rather scarce.
Marleen Adé, Rudy Lauwereins, J. A. Peperst
Added 06 Aug 2010
Updated 06 Aug 2010
Type Conference
Year 1997
Where DAC
Authors Marleen Adé, Rudy Lauwereins, J. A. Peperstraete
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