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DFT
2006
IEEE

Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC

9 years 7 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. The advantages of this approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. Moreover, many of the advanced algorithms, including the independent component analysis, can be systolically mapped to it. The paper discusses these coarse-grain cells in light of a new concept, namely multi-granularity, which simultaneously facilitates defect tolerance and reconfigurability. In particular, it is shown that the multipliers in these J-platform cells can benefit from an innovative block. Called multiplier building block (MBB), it can be used for defect tolerance as well as for configuring larger multipliers, thereby enhancing the yield and computational flexibility. An application...
Vijay K. Jain, Glenn H. Chapman
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where DFT
Authors Vijay K. Jain, Glenn H. Chapman
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