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Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

8 years 10 months ago
Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core
The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption hardware core suited for devices in which low cost and low power consumption are desired. The core constitutes of a novel 8-bit architecture and supports encryption with 128-bit keys. In a 0.13 µm CMOS technology our area optimized implementation consumes 3.1 kgates. The throughput at the maximum clock frequency of 153 MHz is 121 Mbps, also in feedback encryption modes. Compared to previous 8-bit implementations, we achieve significantly higher throughput with corresponding area. The energy consumption per processed block is also lower.
Panu Hämäläinen, Timo Alho, Marko H
Added 11 Jun 2010
Updated 11 Jun 2010
Type Conference
Year 2006
Where DSD
Authors Panu Hämäläinen, Timo Alho, Marko Hännikäinen, Timo D. Hämäläinen
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