Sciweavers

Share
ISVLSI
2007
IEEE

Design of a MCML Gate Library Applying Multiobjective Optimization

10 years 9 months ago
Design of a MCML Gate Library Applying Multiobjective Optimization
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 m technology are presented.
Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfg
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISVLSI
Authors Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfgang H. Krautschneider
Comments (0)
books