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2007
ACM

Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification

9 years 7 months ago
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potential available through MPSoC architectures depends heavily on the effectiveness of this programming. Existing automatic parallelizing techniques, though effective on shared memory architectures, are insufficient for MPSoCs, which are typically characterized by heterogeneous processing elements and memory architectures. The lack of effective automatic techniques requires designers to manually partition the code and the data structures in the reference application to generate a parallel and flexible specification. Manual creation of this model is time consuming and error prone. In this work, we present a novel designer-controlled approach to partition existing code and data structures automatically into a parallel and flexible abstract specification model that can be mapped to a heterogeneous MPSoC. Our results sh...
Pramod Chandraiah, Rainer Dömer
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2007
Where DAC
Authors Pramod Chandraiah, Rainer Dömer
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