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AES
2011
Springer
232views Cryptology» more  AES 2011»
10 years 6 months ago
Reliable performance prediction for multigrid software on distributed memory systems
We propose a model for describing and predicting the parallel performance of a broad class of parallel numerical software on distributed memory architectures. The purpose of this ...
Giuseppe Romanazzi, Peter K. Jimack, Christopher E...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
11 years 10 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ICCD
1999
IEEE
86views Hardware» more  ICCD 1999»
11 years 11 months ago
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications
Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many o...
David L. Landis, Paul T. Hulina, Scott Deno, Luke ...
CODES
2006
IEEE
12 years 22 days ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt
EUROPAR
2007
Springer
12 years 25 days ago
Toward Scalable Matrix Multiply on Multithreaded Architectures
We show empirically that some of the issues that affected the design of linear algebra libraries for distributed memory architectures will also likely affect such libraries for s...
Bryan Marker, Field G. Van Zee, Kazushige Goto, Gr...
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
12 years 29 days ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
DAC
2009
ACM
12 years 1 months ago
PDRAM: a hybrid PRAM and DRAM main memory system
In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges i...
Gaurav Dhiman, Raid Ayoub, Tajana Rosing
DAC
2007
ACM
12 years 7 months ago
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
Pramod Chandraiah, Rainer Dömer
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