Sciweavers

Share
ET
2002

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

9 years 1 months ago
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a program along with compressed test data into the processor's on-chip memory. The processor executes the program which decompresses the test data and applies it to scan chains in the other components of the SOC to test them. The program itself is very simple and compact, and the decompression is done very rapidly, hence this approach reduces both the amount of data that must be stored on the tester and reduces the test time. Moreover, it enables at-speed scan shifting even with a slow tester (i.e., a tester whose maximum clock rate is slower than the SOC's normal operating clock rate). A procedure is described for converting a set of test cubes (i.e., test vectors where the unspecified inputs are left as X's) into a compressed form. A program that can be run on an embedded processor is then given fo...
Abhijit Jas, Nur A. Touba
Added 18 Dec 2010
Updated 18 Dec 2010
Type Journal
Year 2002
Where ET
Authors Abhijit Jas, Nur A. Touba
Comments (0)
books