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SAMOS
2010
Springer
8 years 10 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
ET
2002
72views more  ET 2002»
8 years 11 months ago
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Abstract. A novel approach for using an embedded processor to aid in deterministic testing of the other components of a system-on-a-chip (SOC) is presented. The tester loads a prog...
Abhijit Jas, Nur A. Touba
CSREAESA
2009
9 years 28 days ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
CSREAESA
2006
9 years 1 months ago
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs
Abstract
Daniel T. Milton, Sachin Dhingra, Charles E. Strou...
CSSE
2008
IEEE
9 years 1 months ago
A Power-Efficient Floating-Point Co-processor Design
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
Xunying Zhang, Xubang Shen
ATS
2003
IEEE
100views Hardware» more  ATS 2003»
9 years 3 months ago
A Processor-Based Built-In Self-Repair Design for Embedded Memories
We propose an embedded processor-based built-in self-repair (BISR) design for embedded memories. In the proposed design we reuse the embedded processor that can be found on almost...
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu
CASES
2007
ACM
9 years 3 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
ICCD
1999
IEEE
93views Hardware» more  ICCD 1999»
9 years 4 months ago
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
Abhijit Jas, Nur A. Touba
ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
9 years 4 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
9 years 4 months ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
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