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10

ISMVL
1994
IEEE

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Digital Circuit Verification Using Partially-Ordered State Models

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Digital Circuit Verification Using Partially-Ordered State Models

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Many aspects of digital circuit operation can be efficiently verified by simulating circuit operation over "weakened" state values. This technique has long been practiced with logic simulators, using the value X to indicate a signal that could be either 0

Carl-Johan H. Seger, Randal E. Bryant

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Added	09 Aug 2010
Updated	09 Aug 2010
Type	Conference
Year	1994
Where	ISMVL
Authors	Carl-Johan H. Seger, Randal E. Bryant

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