A dual-core programmable decoder for LDPC convolutional codes

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Abstract— We present the concepts and realization of a highly parallelized decoder architecture for LDPC convolutional codes and tailbiting LDPC convolutional codes. This architecture has a very good scalability and is fully programmable so that it can be applied to several communications and data storage scenarios. The synthesis results show relatively small area consumption for very high decoding speeds.

Marcos B. S. Tavares, Emil Matús, Steffen K

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Data Storage Scenarios | Hardware | ISCAS 2008 | LDPC Convolutional Codes | Parallelized Decoder Architecture |

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Added	31 May 2010
Updated	31 May 2010
Type	Conference
Year	2008
Where	ISCAS
Authors	Marcos B. S. Tavares, Emil Matús, Steffen Kunze, Gerhard Fettweis

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A dual-core programmable decoder for LDPC convolutional codes

Data Storage Scenarios | Hardware | ISCAS 2008 | LDPC Convolutional Codes | Parallelized Decoder Architecture |

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