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2009
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Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches

11 years 12 days ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uniform cache architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this work, we extend that concept with mechanisms that dynamically move data within caches. The key innovation is the use of a shadow address space to allow hardware control of data placement in the L2 cache while being largely transparent to the user application and offchip world. These mechanisms allow the hardware and OS to dynamically manage cache capacity per thread as well as optimize placement of data shared by multiple threads. We show an average IPC improvement of 10-20% for multiprogrammed workloads with capacity allocation policies and an average IPC improvement of 8% for multi-threaded workloads with policies for shared page placement.
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia
Added 25 Nov 2009
Updated 25 Nov 2009
Type Conference
Year 2009
Where HPCA
Authors Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter
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