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EUROPAR
2009
Springer
10 years 4 months ago
Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs
In response to the constant increase in wire delays, Non-Uniform Cache Architecture (NUCA) has been introduced as an effective memory model for dealing with growing memory latenci...
Javier Lira, Carlos Molina, Antonio Gonzále...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
10 years 5 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
HPCA
2007
IEEE
10 years 6 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
HPCA
2009
IEEE
11 years 6 days ago
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
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