40 search results - page 1 / 8 » An Efficient Model for DSP Code Generation: Performance, Cod... |
ISSS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model along with logical propositions is used to create an ...
LCTRTS
2010
Springer
13 years 6 months ago
2010
Springer
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
CASES
2006
ACM
13 years 8 months ago
2006
ACM
When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be ...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
ICIP
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...