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ASPDAC
2010
ACM

Efficient power grid integrity analysis using on-the-fly error check and reduction

10 years 19 days ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reduction technique to reduce the circuit matrices before the simulation. Due to the disruptive nature of tap current waveforms in typical industry power grid networks, input current sources typically has wide frequency power spectrum. To avoid the excessively sampling, the new approach introduces an error check mechanism and on-the-fly error reduction scheme during the simulation of the reduced circuits to improve the accuracy of estimating the the large IR drops. The proposed method presents a new way to combine model order reduction and simulation to achieve the overall efficiency of simulation. The new method can also easily trade errors for speed for different applications. Experimental results show the proposed IR drop analysis method can significantly reduce the errors of the existing ETBR method at the simila...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
Added 10 Feb 2011
Updated 10 Feb 2011
Type Journal
Year 2010
Where ASPDAC
Authors Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
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