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CSREAESA
2009

Embedded Processor Based Fault Injection and SEU Emulation for FPGAs

9 years 11 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip (SoC) implementations. The case studies include embedded hard core and soft core processors which manipulate configuration memory bits to emulate physical and transient faults in the FPGA core including shorts and opens in programmable interconnect and many different faults in logic resources. The emulated faults are used to evaluate fault detection capabilities of Built-In Self-Test (BIST) approaches, including fault identification capabilities of diagnostic procedures, and to evaluate the effect of Single Event Upsets (SEUs), including their detection and correction. Embedded processor based approaches provide significant improvement over previous fault injection techniques and, in turn, enable a more thorough analysis of BIST, diagnosis, and SEU mitigation.1
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,
Added 09 Nov 2010
Updated 09 Nov 2010
Type Conference
Year 2009
Where CSREAESA
Authors Bradley F. Dutton, Mustafa Ali, Charles E. Stroud, John Sunwoo
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