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DATE
2009
IEEE

Enabling concurrent clock and power gating in an industrial design flow

9 years 6 months ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way that the clock-gating information can be used to drive the control signal of the power-gating circuitry, thus providing additional leakage minimization conditions w.r.t. those manually inserted by the designer. This conceptual integration, however, poses several challenges when moved to industrial design flows. Although both clock and power-gating are supported by most commercial synthesis tools, their combined implementation requires some flexibility in the back-end tools that is not currently available. This paper presents a layout-oriented synthesis flow which integrates the two techniques and that relies on leading-edge, commercial EDA tools. Starting from a gated-clock netlist, we partition the circuit in a number of clusters that are implicitly determined by the groups of cells that are clock-gated by ...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
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