Enhanced LEON3 core for superscalar processing

Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-on-Chip (SoC) evolution. The paper presents the methodology of enhancing LEON3 processor IP core with superscalar abilities for low-power or high-performance systems. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle with only one third increase in area occupation. The Enhanced LEON3 IP core was synthesized using UMC 90 nm CMOS technology.

• Type: Conference
• Year: 2009
• Where: DDECS
• Authors: Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz
• Keywords: DDECS 2009, Hardware, IP Core, Modern Microprocessor Architectures, Processor Ip Core