Evaluating Hardware Compilation Techniques

Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable computing systems since they provide a fast, easy to use, “software-like” programming environment for users with little hardware design experience. We compare three hardware compilation techniques. First, we study sequential compilation, which produces hardware that evaluates each assignment of the source program in one clock cycle. Next, we evaluate the effects of local parallelizing optimizations. Finally, we apply pipeline vectorization, a method based on software vectorization for synthesizing hardware pipelines, which exploits hardware parallelism globally. Results of all three techniques for several benchmark programs are presented and discussed. Pipeline vectorization has been found to speedup hardware implementations of vectorizable programs by up to two orders of magnitude, whereas local optimiz...

• Type: Conference
• Year: 2000
• Where: FCCM
• Authors: Markus Weinhardt, Wayne Luk
• Keywords: FCCM 2000, Hardware Compilation Techniques, Pipeline Vectorization, Sequential Compilation, VLSI