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2009
IEEE

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

9 years 5 months ago
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust against DEMA.
Victor Lomné, Philippe Maurine, Lionel Torr
Added 16 Aug 2010
Updated 16 Aug 2010
Type Conference
Year 2009
Where DATE
Authors Victor Lomné, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans
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