Exploiting Prediction to Reduce Power on Buses

We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified SimpleScalar simulator and SPEC benchmarks. We show an average of 35% savings in transitions on internal buses. To quantify actual power savings, we design a dictionary based encoder/decoder circuit in a 0.13?m process, extract it as a netlist, and simulate its behavior under SPICE. Utilizing a realistic wire model with repeaters, we show that we can break even at median wire length scales

• Type: Conference
• Year: 2004
• Where: HPCA
• Authors: Victor Wen, Mark Whitney, Yatish Patel, John Kubiatowicz
• Keywords: Actual Power Savings, Computer Architecture, HPCA 2004, Median Wire Length, Simple Coding Schemes