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DATE
2003
IEEE

Exploring SW Performance Using SoC Transaction-Level Modeling

9 years 5 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the SoC platform. The SoC provider provides a cycle-accurate functional model of the SoC architecture using the basic SystemC Transaction Level Modeling (TLM) components provided by VISTA : bus models, memories, IPs, CPUs, and RTOS generic services. These components have been carefully designed to be integrated into a SoC design flow with an implementation path for automatic generation of IP HW interfaces and SW device drivers. The application developer can then integrate the application code onto the SoC architecture as a set of SystemC modules. VISTA supports cross-compilation on the target processor and back annotation, therefore bypassing the use of an ISS. We illustrate the features of VISTA through the design and simulation of an MPEG video decoder application.
Imed Moussa, Thierry Grellier, Giang Nguyen
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where DATE
Authors Imed Moussa, Thierry Grellier, Giang Nguyen
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