A Fast FPGA Implementation of a General Purpose Neuron

The implementation of larger digital neural networks has not been possible due to the real-estate requirements of single neurons. We present an expandable digital architecture which allows fast and spacee cient computation of the sum of weighted inputs, providing an e cient implementation base for large neural networks. The actual digital circuitry is simple and highly regular, thus allowing very e cient space usage of ne grained FPGAs. We take advantage of the re-programmability of the devices to automatically generate new custom hardware for each topology of the neural network.

• Type: Conference
• Year: 1994
• Where: FPL
• Authors: Valentina Salapura, Michael Gschwind, Oliver Maischberger
• Keywords: Digital Neural Networks, FPL 1994, Hardware, Large Neural Networks, Neural Network