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2003
IEEE

A fast parallel reed-solomon decoder on a reconfigurable architecture

10 years 7 days ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. Numerous modifications of the first-generation of the architecture have made a scalable computation and communication intensive architecture capable of extracting parallelisms of fine grain in instruction level. Many algorithms and the whole Digital Video Broadcasting base-band receiver as well, have been mapped onto the second architecture with impressing performance. The mapping of a Reed-Solomon decoder proposed in this paper highly parallelizes all of its sub-algorithms, including Syndrome Computation, Berlekamp Algorithm, Chein Search, and Error Value Computation, in a SIMD fashion. The mapping is tested on a cycle-accurate simulator, “Mulate”, and the performance is encouragingly better than other architectures. The decoding speed of the RS ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where CODES
Authors Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
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