Fpga-based face detection system using Haar classifiers

This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also we discuss the optimization of the proposed architecture which can be scalable for configurable devices with variable resources. The proposed architecture for face detection has been designed using Verilog HDL and implemented in Xilinx Virtex-5 FPGA. Its performance has been measured and compared with an equivalent software implementation. We show about 35 times increase of system performance over the equivalent software implementation. Categories and Subject Descriptors C.3 [Special-Purpose and Application-Based Systems]: RealTime and Embedded Systems General Terms Design, Experimentation, Measurement, Performance Key...

• Type: Conference
• Year: 2009
• Where: FPGA
• Authors: Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner
• Keywords: Equivalent Software Implementation, Face Detection, Face Detection System, FPGA 2009, Hardware