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APCSAC
2006
IEEE

Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays

12 years 5 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affect the performance of sequential code sequences. We propose dealing with these delays through a dynamic functional unit chaining approach. We study the performance benefits of a superscalar, out-of-order processor augmented with a two-by-two array of ALUs interconnected by a fast, partial bypass network. An online profiler guides the automatic configuration of the network to accelerate specific patterns of dependent instructions. A detailed study of benchmark simulations demonstrates these first steps towards mapping binaries to a small coarse-grained array at runtime can improve instruction throughput by over 18% and 25% when the microarchitecure includes bypass delays of one cycle and two cycles, respectively.
Lih Wen Koh, Oliver Diessel
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where APCSAC
Authors Lih Wen Koh, Oliver Diessel
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