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ICCAD
2002
IEEE

Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

11 years 1 months ago
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-processing step that provides an effective set of initial Lagrange multipliers. Compared to the previous Lagrangian-based approach, Forge is considerably faster and does not have the inefficiencies due to difficult-todetermine initial conditions and constant factors. We compared the two algorithms on 30 benchmark designs, on a Sun UltraSparc-60 workstation. On average Forge is 200 times faster than the previously published algorithm. We then improved Forge by incorporating a slew-rate-based convex delay model, which handles distinct rise and fall gate delays. We show that Forge is 15 times faster, on average, than the AMPS transistor-sizing tool from Synopsys, while achieving the same delay targets and using similar total transistor area.
Hiran Tennakoon, Carl Sechen
Added 17 Mar 2010
Updated 17 Mar 2010
Type Conference
Year 2002
Where ICCAD
Authors Hiran Tennakoon, Carl Sechen
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