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ICCAD
1997
IEEE
89views Hardware» more  ICCAD 1997»
9 years 5 months ago
Optimal shape function for a bi-directional wire under Elmore delay model
In this paper, we determine the optimal shape function for a bi-directional wire under the Elmore delay model. Given a bi-directional wire of length L, let fx be the width of the ...
Youxin Gao, D. F. Wong
ICCAD
1994
IEEE
90views Hardware» more  ICCAD 1994»
9 years 5 months ago
Low-cost single-layer clock trees with exact zero Elmore delay skew
We give the rst single-layer clock tree construction with exact zero skew according to the Elmore delay model. The previous Linear-Planar-DME method 11 guarantees a planar solutio...
Andrew B. Kahng, Chung-Wen Albert Tsao
ICCAD
1996
IEEE
74views Hardware» more  ICCAD 1996»
9 years 5 months ago
Optimal non-uniform wire-sizing under the Elmore delay model
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area...
Chung-Ping Chen, Hai Zhou, D. F. Wong
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
9 years 5 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
ISPD
1999
ACM
95views Hardware» more  ISPD 1999»
9 years 5 months ago
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Yanhong Yuan, Prithviraj Banerjee
ISCAS
2006
IEEE
82views Hardware» more  ISCAS 2006»
9 years 7 months ago
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny
ICCAD
2002
IEEE
149views Hardware» more  ICCAD 2002»
9 years 10 months ago
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
Hiran Tennakoon, Carl Sechen
ICCD
2002
IEEE
140views Hardware» more  ICCD 2002»
9 years 10 months ago
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
Arif Ishaq Abou-Seido, Brian Nowak, Chris C. N. Ch...
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
9 years 10 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...
DAC
2006
ACM
10 years 2 months ago
Elmore model for energy estimation in RC trees
This paper presents analysis methods for energy estimation in RC trees driven by time-varying voltage sources, e.g., buffers, timevarying power supplies, and resonant clock genera...
Quming Zhou, Kartik Mohanram
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