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ICCAD
2002
IEEE
126views Hardware» more  ICCAD 2002»
13 years 8 months ago
Robust and passive model order reduction for circuits containing susceptance elements
Numerous approaches have been proposed to address the overwhelming modeling problems that result from the emergence of magnetic coupling as a dominant performance factor for ICs a...
Hui Zheng, Lawrence T. Pileggi
ICCAD
2002
IEEE
82views Hardware» more  ICCAD 2002»
13 years 8 months ago
Hardware/software partitioning of software binaries
Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent ...
Greg Stitt, Frank Vahid
ICCAD
2002
IEEE
85views Hardware» more  ICCAD 2002»
13 years 8 months ago
On undetectable faults in partial scan circuits
We study the undetectable faults in partial scan circuits under a test application scheme referred to as transparent-scan. The transparent-scan approach allows very aggressive tes...
Irith Pomeranz, Sudhakar M. Reddy
ICCAD
2002
IEEE
160views Hardware» more  ICCAD 2002»
13 years 8 months ago
Folding of logic functions and its application to look up table compaction
The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic func...
Shinji Kimura, Takashi Horiyama, Masaki Nakanishi,...
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
13 years 8 months ago
Efficient mixed-domain analysis of electrostatic MEMS
—We present efficient computational methods for scattered point and meshless analysis of electrostatic microelectromechanical systems (MEMS). Electrostatic MEM devices are govern...
Gang Li, Narayan R. Aluru
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
13 years 8 months ago
Optimal buffered routing path constructions for single and multiple clock domain systems
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
13 years 8 months ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
ICCAD
2002
IEEE
74views Hardware» more  ICCAD 2002»
13 years 8 months ago
The A to Z of SoCs
Reinaldo A. Bergamaschi, John M. Cohn
ICCAD
2002
IEEE
89views Hardware» more  ICCAD 2002»
13 years 8 months ago
Free space management for cut-based placement
IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia