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ASPDAC
1999
ACM

Generation of Interpretive and Compiled Instruction Set Simulators

9 years 2 months ago
Generation of Interpretive and Compiled Instruction Set Simulators
Abstract Due to the large variety of di erent embedded processor types, retargetable software development tools, such as compilers and simulators, have received attention recently. Retargetability allows to handle di erent target processors with a single tool. In this paper, we present a system for automatic generation of instruction set simulators for a class of embedded processors. Retargetability is achieved by automatic generation of simulators from processor descriptions, given as behavioral or RT-level HDL models. The presented system is capable of bit-true simulation for arbitrary processor word lengths, and it generates both interpretive or compiled simulators. Experimental results for di erent processors indicate comparatively high simulation speed.
Rainer Leupers, Johann Elste, Birger Landwehr
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where ASPDAC
Authors Rainer Leupers, Johann Elste, Birger Landwehr
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