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2000
IEEE

On the Generation of Multiplexer Circuits for Pass Transistor Logic

11 years 10 months ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, performance and power consumption. Existing automatic PTL synthesis tools use a direct mapping of (decomposed) BDDs to pass transistors. Thereby, structural properties of BDDs like the ordering restriction and the fact that the select signals of the multiplexers (corresponding to BDD nodes) directly depend on input variables, are imposed on PTL circuits although they are not necessary for PTL synthesis. General Multiplexer Circuits can be used instead and should provide a much higher potential for optimization compared to a pure BDD approach. Nevertheless – to the best of our knowledge – an optimization of general Multiplexer Circuits (MCs) for PTL synthesis was not tried so far due to a lack of suitable optimization approaches. In this paper we present such an algorithm which is based on efficient BDD optim...
Christoph Scholl, Bernd Becker
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2000
Where DATE
Authors Christoph Scholl, Bernd Becker
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