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DSD
2010
IEEE
149views Hardware» more  DSD 2010»
11 years 9 months ago
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures
Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace i...
Marcus Jeitler, Jakob Lechner
CSREAESA
2006
12 years 1 months ago
Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy
- Triple Modular Redundancy is widely used in dependable systems design to ensure high reliability against soft errors. Conventional TMR is effective in protecting sequential circu...
Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wan...
DSN
2005
IEEE
12 years 1 months ago
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors an...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
DAC
2005
ACM
12 years 1 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...
ASPDAC
2008
ACM
117views Hardware» more  ASPDAC 2008»
12 years 1 months ago
Dependability, power, and performance trade-off on a multicore processor
- As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A na
Toshinori Sato, Toshimasa Funaki
USENIX
2007
12 years 2 months ago
A Memory Soft Error Measurement on Production Systems
Memory state can be corrupted by the impact of particles causing single-event upsets (SEUs). Understanding and dealing with these soft (or transient) errors is important for syste...
Xin Li, Kai Shen, Michael C. Huang, Lingkun Chu
ASPDAC
2006
ACM
96views Hardware» more  ASPDAC 2006»
12 years 3 months ago
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand...
DATE
2010
IEEE
165views Hardware» more  DATE 2010»
12 years 4 months ago
Multicore soft error rate stabilization using adaptive dual modular redundancy
— The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can ...
Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson...
ITC
2003
IEEE
141views Hardware» more  ITC 2003»
12 years 5 months ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba
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