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ISCAS
2007
IEEE

Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories

9 years 7 months ago
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories
— We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing incidence particle strikes, which produce disruptions with the widest possible spatial separation. Advantages with respect to size, complexity, and MBU tolerance are realized when this approach is compared to existing solutions.
Daniel R. Blum, José G. Delgado-Frias
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Daniel R. Blum, José G. Delgado-Frias
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