Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories

— We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing incidence particle strikes, which produce disruptions with the widest possible spatial separation. Advantages with respect to size, complexity, and MBU tolerance are realized when this approach is compared to existing solutions.

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Daniel R. Blum, José G. Delgado-Frias
• Keywords: Incidence Particle Strikes, ISCAS 2007, Multiple-node Disruption Tolerant, Possible Spatial Separation