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ISCAS
2011
IEEE

Hardware synchronization for embedded multi-core processors

8 years 6 months ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establishing coherence and consistency for different types of shared memory by hardware means. Also support for point-to-point synchronization between the processor cores is realized implementing different hardware barriers. The practical examinations focus on the logical first step from single- to dual-core systems, using an FPGA-development board with two hard PowerPC processor cores. Best- and worst-case results, together with intensive benchmarking of all synchronization primitives implemented, show the expected superiority of the hardware solutions. It is also shown that dual-ported memory outperforms single-ported memory if the multiple cores use inherent parallelism by locking s...
Christian Stoif, Martin Schoeberl, Benito Liccardi
Added 21 Aug 2011
Updated 21 Aug 2011
Type Journal
Year 2011
Where ISCAS
Authors Christian Stoif, Martin Schoeberl, Benito Liccardi, Jan Haase
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