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Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

9 years 2 months ago
Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated. Categories and Subject Descriptors B.5.2 [Register-Transfer-Level Implementation]: Design Aids
Hyunuk Jung, Soonhoi Ha
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where CODES
Authors Hyunuk Jung, Soonhoi Ha
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